Stanford Seminar - Neural Networks on Chip Design from the User Perspective
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Overview
Explore the cutting edge of neural networks in chip design, focusing on user perspectives, at the upcoming Stanford Seminar. This session delves into the evolution of customized hardware architectures designed to enhance the energy efficiency of deep learning inference processing. With a keen eye on integrating emerging Non-Volatile Memory (NVM) technology, the seminar promises insights into in-memory computing's potential, appealing to both academic and industry interests. We will revisit our contributions to Deep Learning Processing Unit (DPU) design on FPGA platforms within Tsinghua University and Deephi. The discussion will extend to introducing user-centric features like interrupt and virtualization into accelerators. Additionally, the seminar will address the critical challenges of ensuring reliability and security in neural network (NN) accelerators, shedding light on preliminary solutions for issues encountered with FPGA and NVM technologies. Join us for this enlightening session presented by Stanford University, now available on YouTube. Ideal for enthusiasts and professionals interested in Neural Networks and FPGA courses.